1. Field of the Invention
The present invention relates generally to field effect transistors, and more particularly to a field effect transistor with a double sided airbridge.
2. Description of the Prior Art
A conventional field effect transistor (hereinafter referred to as an FET) includes a semiconductor substrate (reference numeral 1 in FIGS. 1a and 1b) with conductive layers or insulating layers disposed on the substrate. A gate electrode is provided to modulate the current flowing through a channel from a drain electrode to a source electrode in response to a radio frequency (RF) electrical signal applied thereto. Most commonly, the gate is fed from the end with the RF modulating signal which travels the length of the gate stripe.
One use of such an FET is as a low noise amplifier. An example of an FET is shown in FIG. 1 and found in IEEE Transactions On Electron Devices, Vol. ED-31, No. 12, Dec. 1985, pgs. 2754-2759, "Airbridge Gate FET For GaAs Monolithic Circuits". In such article a single airbridge structure 6 is formed over the source electrode 4. The airbridge 6 is T-shaped in plan view and connects the relatively small gate pad 2b at the base of the T at one side of the source strip contact 4 and the narrow gate finger electrode 2a along its whole width at the top of the T. Electric power is supplied to the small stepped gate pad 2b in the FET with the current flowing through outwardly fanned paths to the much wider gate finger electrode 2a. However, the airbridge 6 and the source electrode 4 cross each other over a large area as shown in FIG. 1a. Thus, even though an airbridge structure is used, an increase in gate capacitance is created which decreases performance at high frequencies. More importantly, during fabrication of the single airbridge, a large stress is exerted on the extremely narrow gate finger 2a. This stress can be considered visually as a force vector angled upwards and to the right on the junction of the gate finger 2a and the substrate 1 as shown in FIG. 1b. Thus, this large force applied to the small gate finger junction area results in extreme stress exerted on the relatively small base portion of gate finger. This reaction reduces the relatively weak gate finger structural bond with the substrate so that the metal gate structure tends to lift off during fabrication of the FET. Also, the electrical resistance of the single airbridge gate is significant which decreases the cut-off frequency of the FET.
Another example of a field effect transistor is illustrated in FIG. 2, and found in U.S. Pat. No. 5,019,877, "Field Effect Transistor", by Kenji Hosogi. In such patent the field effect transistor with its substrate 1, drain electrode 3 and source electrode 4 includes a narrow airbridge wiring structure 6 that resembles a raised narrow elongated conductor which connects adjacent feeding points 5 on a gate finger 2a longitudinally along the width of the airbridge. Although the narrow airbridge with its narrow footprint reduces resistance and capacitance of the structure, such an FET, however, has a propagation time delay and a relatively high gate resistance.
What is needed, therefore, is an FET in which includes an airbridge portion of a gate electrode that reduces the structural stress on the relatively small central gate finger portion and which provides a lower gate resistance.